Master slice type semiconductor integrated circuits, such as, for example, gate arrays and embedded arrays, are manufactured using an unfinished wafer (master slice) in which those process steps to be performed before the metal wiring step are completed. The master slice is wired according to specific circuit functions required by the user and coated with a protection film, to thereby provide a finished wafer. Unfinished wafers may be stocked such that the delivery time is shortened to deliver semiconductor integrated circuits to customers.
Prior to manufacturing master slice type semiconductor integrated circuits, an unfinished wafer having basic cells arranged in a matrix is prepared in advance. Provision of through holes and placement and wiring of metal wiring layers to the unfinished wafer are automatically performed by an automatic placing and routing apparatus.
There is a growing tendency in which the number of metal wiring layers is increased, for example, from the two-layer to the three-layer and to the four-layer. The bottommost or first metal wiring layers in a semiconductor integrated circuit of the type described above are used as signal input wirings for inputting signals to gates of MOS transistors that form basic cells, power supply wirings for supplying power to sources thereof and signal output wirings for outputting signals from drains thereof, for example. These wirings are connected to the gates, sources or drains through contacts. Also, first metal wiring layers may be used as power source wirings for supplying power source voltages, such as potentials VDD and VSS, and signal wirings that provide connections within basic cells and between basic cells. Other metal wiring layers, such as second and third metal wiring layers, are used mainly as signal wirings.
Aluminum layers are generally used as metal wiring layers. For example, a two-layer metal wiring layer may include a first Al wiring and a second Al wiring. When wiring routes of the first and second Al layers are determined by an automatic placing and routing apparatus, priority wiring directions are respectively assigned to the first and second Al wirings.
It is noted that it is more difficult to miniaturize a master slice type semiconductor integrated circuit having a plurality of metal wiring layers compared to a standard cell type that is designed using basic cells registered in a library.
For example, let us consider one wiring example in which a signal wiring is externally lead out from a region between two power source wirings in the first layer (VDD, VSS) that are formed in a first priority wiring direction, for example. In this case, if the two power source wirings and the signal wiring are formed with the first layers, they are short-circuited. In order to cross over the power source wirings formed in the first priority wiring direction, the signal wiring has to be formed with a first layer signal wiring, a second layer signal wiring and a via that connects the first and second layer signal wirings. The second layer signal wiring is used only to cross over the first power source wiring. As a consequence, other wirings cannot be formed in such a region in the second layer. The other wirings in the second layer may need to take a detour. In this manner, the routing resource for the second layer is exhausted.
For the convenience of explanation, let us assume, for example, there are 100 lateral lines×100 vertical lines of lattice grids in a three-layer metal wiring structure, and the priority wiring direction for the first and third layers is the lateral direction and the priority wiring direction for the second layer is the vertical direction. In this case, while the first and third layers provide a total of 200 wiring lines in the lateral direction as the routing resource, the second layer provides 100 wiring lines in the vertical direction as the routing resource.
It is noted that the placement of the metal wirings in the first layer is mostly determined by the placement of basic cells, and the number of usable wiring lines is determined as a matter of course. Therefore, if the wirings in the second and third layers are disposed in a well-balanced manner, the size of the chip can reduced. However, as described above, if the wirings in the second layer are used to cross over the wirings in the first layer, the wiring efficiency of the second layer deteriorates.
In addition, when a roundabout routing of wirings is implemented by connecting a plurality of layers with vias, or a roundabout routing of wirings is made within the same layer, the wiring length increases. Moreover, in recent years, the line width has become narrower as the semiconductor manufacturing process has become more miniaturized. As a result, the resistance of the wiring per unit length tends to increase. Because of these two major factors, problems arise in that the wiring resistance is increased, and the signal delay is thus increased.
In solving these problems, the inventors of the present application have paid attention to the fact that the wiring resource of metal wiring layers and, in particular, the wiring resource of second metal wiring layers are not effectively utilized.
It is an object of the present invention to provide a master slice type semiconductor integrated circuit and a design method therefor that make an effective use of the wiring resource of metal wiring layers to thereby increase the wiring efficiency and reduce the chip size.
Another object of the present invention is to provide a master slice type semiconductor integrated circuit and a design method therefor that prevent the increase in the wiring resistance and reduce the signal delay as much as possible by making an effective use of the wiring resource of metal wiring layers to thereby increase the wiring efficiency.